1. Field of the Invention
The present invention relates to a compensation circuit, and more particularly to a memory with compensation circuit.
2. Description of the Related Art
With the growth in the use of portable electronic devices, the desire for non-volatile memory has increased. Among the various kinds of non-volatile, memory, phase change memory is the most competitive next generation non-volatile memory due to its higher speed, lower power consumption, higher capacity, reliability, easier process integration and lower cost. The operation of the phase change memory is mainly achieved by inputting two current pulses with different current magnitudes to the phase change memory. When the phase change memory receives the current pulses, the phase change memory is heated due to Ohm's Law, and the material of the phase change memory therefore transforms to an amorphous state or a crystalline state according to the temperature of the phase change memory. The amorphous state and the crystalline state are reversible and data storage can be achieved by different resistances of the material of the phase change memory at the amorphous state and the crystalline state.
The phase change memory comprises a plurality of writing paths, and each writing path comprises a plurality of phase change memory cells (PCM cells), or so-called GST device, to form a memory array arranged in matrix form. When writing data to the phase change memory, writing current is inputted to a selected writing path via a driving circuit, and the writing current is then inputted to the desired PCM cell via a selector. However, the driving ability of the writing current may decrease due to a voltage drop generated in the current transmission in the writing path. The voltage drop is caused by an equivalent resistor of the conduct line between the driving circuit and the desired PCM cell. Sometimes resulting in the PCM cell at the near side of the driving circuit being accessed normally and the PCM cell at the far side of the driving circuit being accessed abnormally due to insufficient writing current. If the PCM cell receives insufficient writing current, the PCM cell will be incompletely crystallized.
Referring to FIG. 1. FIG. 1 is a schematic diagram of a writing path for a conventional phase change memory device. The writing driver 11 receives a control signal to output a writing current with fixed magnitude to the writing path. The writing current is then transmitted to the corresponding GST device based on the select signals G1 to Gn and selector 12_1 to 12—n. The equivalent resistor, such as the resistor R1 to Rn, is generated in the writing path and the resistance of the equivalent resistor is determined based on, the distance between the corresponding GST device and the writing driver 11. The equivalent resistor causes unnecessary voltage loss and this decreases the driving ability of the writing current. If the PCM cell is at the far side of the writing driver 11, such as a GST device 13—n, the PCM cell may be incompletely crystallized or amorphous due to insufficient writing current.
Conventionally, to solve this problem, the common technique utilized is to increase the magnitude of the writing current, but this may cause the PCM cell which is at the near side of the writer 11, such as the GST device 13_1, of being over-crystallized or over-amorphous. When the described GST device 13_1 is accessed a following time, the GST device 13_1 may be incompletely crystallized or amorphous, or the GST device 13_1 may require larger voltage to be completely crystallized or amorphous. Furthermore, if the GST device 13_1 is incompletely crystallized or amorphous, the resistance of the GST device 13_1 at the crystallized state increases and this reduce the range of sensing margin.